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TC94A04AFG/AFDG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A04AFG,TC94A04AFDG
1 chip Audio Digital Processor
TC94A04AFG/AFDG is a single-chip audio Digital Signal Processor, incorporating 4 way stereo analog switch, 2 ch AD converter, 4 ch DA converter, and electronic volume for trimming. It is possible to realize many applications, such as sound field control -hall simulation, for example-, digital filter for equalizers, surround, base boost and something.
TC94A04AFG
Features
* * * * * * Incorporates a 4 ch-stereo analog switch for AD converter input. Incorporates a 1 ch stereo line-out. Incorporates a 1 bit -type AD converter (two channels). THD: -82dB (typ.) S/N: 95dB (typ.) Incorporates a 1 bit -type DA converter (four channels). THD: -86dB (typ.) S/N: 98dB (typ.) Incorporates a trimming analog volume for each output of DA converter. 0dB to -24dB (1dB step) As digital input/output port, this has 3 input port (6 ch) and 1 output port (2 ch), enabling input/output of sampling of 96 kHz/24 bit. Incorporates a built-in digital de-emphasis filter. Incorporates a digital attenuator.
P-QFP80-1420-0.80M P-QFP60-1414-0.80N TC94A04AFDG
* * *
Weight P-QFP60-1414-0.80N : 1.08 g (typ.) P-QFP80-1420-0.80M: 1.57 g (typ.)
Incorporates a boot ROM to set a coefficient automatically, which enables to transfer an initial data from built-in ROM/RAM to registers at the time of resetting Boot ROM: 512 words The DSP block specifications are as follows: Data bus: 24 bits Multiplier/adder: 24 bits x 16 bits + 43 bits 43 bits Accumulator: 43 bits (sign extension: 4 bits) Program ROM: 1024 words x 32 bits Coefficient RAM: 384 words x 16 bits Coefficient ROM: 256 words x 16 bits Offset RAM: 16 words x 11 bits Data RAM: 256 words x 24 bits Interface buffer RAM: 32 words x 16 bits Operation speed: 22.5 MIPS (510 step/fs: master clock = 768 fs, fs = 44.1 kHz) Note 1: At the time of an analog input, approximately 170 steps (85 step/ch) in 510 step are used for the operation of the decimation filter for AD converters. Incorporates data delay RAM (32 kbits). Delay RAM: 2048 words x 16 bits (32 kbits) The microcontroller interface can be selected between Toshiba original 3 line mode and I2C mode. CMOS silicon structure supports high speed. Power supply is a single 5 V. The package are 60-pin and 80 pin flat package.
*
* * * * *
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TC94A04AFG/AFDG
Block Diagram/Pin Connection
TC94A04AFG
DOUT TST1 TST0 IFDO DIN0 DIN1 DIN2 32 31 GND IFCK I2CS ERR RST VDD 36 35 IFDI
45
44
43
42
41
40
39
38
CS 37
34
33
LIN4 46 LIN3 47 LIN2 48 LIN1 49 RIN4 50 RIN3 51 RIN2 52 RIN1 53 GNDAL 54 OUTL 55 VRAL 56 VDALR 57 VRAR 58 OUTR 59 GNDAR 60
19 k
C1
C1 Lch input Mute SW
MCU Interface Audio serial interface
EBCI/O 30 ELRI/O 29 SYNC 28
19 k
C2
C2
19 k
C3
20 k 500
C3
19 k
C4
C4
GNDR 27 Delay RAM VDDR 26 GNDA4 25 AI4 24 AO4 23 AOT4 22 VDA34 21 Ch3 DAC circuit AOT3 20 AO3 19 AI3 18 20 k 41.5 k Same as Ch1 DAC circuit 8 k GNDA3 17 VRO2 16 BP BP
VRAL
Rch input 500 Same as Lch input circuit
DSP (I/O Interface) Ch4 DAC circuit Same as Ch1 DAC circuit
27 k
ADC VRAL Lch circuit 41.5 k 15 k 15 k 15 k DAC 15 k 15 k 15 k Ch1 DAC circuit Ch2 DAC Circuit
Same as Ch1 DAC circuit
Same as Lch circuit 27 k
Oscillator circuit
7.8 k 6 7 8
VDA12
XI
AOT1
AOT2
AO1
AO2
GNDA1
BP
BP
2
GNDA2
XO GNDX
VRO1
VDX
VRI
AI1
AI2
1
2
3
4
5
4 k 9
10
11
12
13
14
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TC94A04AFG/AFDG
TC94A04AFDG
DOUT EBCI/O 42 41 TST1 TST0 IFDO
IFCK
DIN0
DIN1
DIN2
GND
I2CS
ERR
RST
VDD
IFDI
NC
NC
NC
NC
NC
NC
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
CS
LIN4 65 LIN3 66 LIN2 67 LIN1 68 RIN4 69 RIN3 70 RIN2 71 RIN1 72 NC 73 GNDAL 74 OUTL 75 VRAL 76 NC 77 VDALR 78 VRAR 79 OUTR 80
19 k
C1
C1 Lch input Mute SW MCU Interface Audio serial interface
ELRI/O 40 SYNC 39 GNDR 38 500 VDDR 37 Delay RAM NC 36 GNDA4 35 500 DSP (I/O Interface) NC 34 Ch4 DAC circuit AI4 33 AO4 32 NC 31 BP
19 k
C2
C2
19 k
C3
20 k
C3
19 k
C4
C4
VRAL
Rch input Same as Lch input circuit
Same as Ch1 DAC circuit
27 k Ch3 DAC circuit ADC VRAL Lch circuit 15 k 15 k 15 k DAC 15 k 15 k 15 k Ch1 DAC circuit Ch2 DAC circuit Same as Ch1 DAC circuit
AOT4 30 NC 29 VDA34 28 AOT3 27 20 k 41.5 k Same as Ch1 DAC circuit 8 k AO3 26 AI3 25 BP
27 k
Same as Lch circuit
Oscillator circuit
41.5 k
7.8 k
VDA12
XI
GNDAR
VRI
NC
NC
NC
NC
NC
AOT1
AOT2
AO1
AO2
AI1
AI2
NC
VRO2
VDX
VRO1
GNDA1
BP
BP
GNDA3
XO GNDX
GNDA2
1
2
3
4
5
6
7
8
9
10
11
4 k 12
13
14
15
16
17
18
19
20
21
22
23
24
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TC94A04AFG/AFDG
Pin Functions
Pin No. TC94A 04AFG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TC94A 04AFDG (Note 3) 2 3 4 5 7 8 9 11 13 14 15 17 18 20 21 23 24 25 26 27 28 30 32 33 35 37 38 39 Symbol I/O Function Remarks
VDX XI XO GNDX GNDA1 AI1 AO1 AOT1 VDA12 AOT2 AO2 AI2 GNDA2 VRO1 VRI VRO2 GNDA3 AI3 AO3 AOT3 VDA34 AOT4 AO4 AI4 GNDA4 VDDR GNDR SYNC
I O I O O O O I O I O I O O O O I I
Power pin for oscillator circuit Crystal oscillator connecting or clock input pin Crystal oscillator connecting pin Ground pin for crystal oscillator circuit. Analog ground pin for DAC-Lch DAC-Lch attenuator input pin DAC-Lch signal output terminal DAC-Lch attenuator output pin Analog power pin for DAC-L/Rch DAC-Rch attenuator output pin DAC-Rch signal output pin DAC-Rch attenuator input pin Analog ground terminal for DAC-Rch Reference voltage output pin-1 for DAC Reference voltage pin for DAC Reference voltage output pin-2 for DAC Analog ground pin for DAC-Cch DAC-Cch attenuator input pin DAC-Cch signal input pin DAC-Cch attenuator output pin Analog power pin for DAC-C/Sch DAC-Sch signal output pin DAC-Sch signal output pin DAC-Sch attenuator input pin Analog ground pin for DAC-Sch Power pin for delay RAM Ground pin for delay RAM Program SYNC signal input pin Schmitt input, TTL/CMOS (Note 2) Schmitt input, TTL/CMOS (Note 2) Schmitt input, TTL/CMOS (Note 2) Schmitt input, TTL/CMOS (Note 2)
29
40
ELRI/O
I/O
LR clock input/output pin for serial data (DIN/DOUT)
30
41
EBCI/O
I/O
Bit clock input/output pin for serial data (DIN/DOUT)
31
43
DIN2
I
Serial data input pin 2
Note 2: 28 to 33 pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are 39 to 41 pins and 43 to 46 pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
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TC94A04AFG/AFDG
Pin No. TC94A 04AF TC94A 04AFD (Note 3) 45 Symbol I/O Function Remarks
32
DIN1
I
Serial data input pin 1
Schmitt input, TTL/CMOS (Note 2) Schmitt input, TTL/CMOS (Note 2)
33 34 35 36
37
38 39 40 41
46 48 49 50
52
53 54 55 57
DIN0 DOUT VDD
RST
CS IFCK IFDI IFDO
I O
I
I I I/O O
Serial data input pin 0 Serial data output pin Power pin
Reset pin
Microcontroller interface chip select signal input pin Microcontroller interface data shift clock input pin Microcontroller interface data input/output pin (I C bus) Microcontroller interface data output pin
2
Schmidt input
Schmidt input Schmidt input Schmidt input
ERR I2CS GND TST0 TST1 LIN4 LIN3 LIN2 LIN1 RIN4 RIN3 RIN2 RIN1 GNDAL OUTL VRAL VDALR VRAR OUTR GNDAR
O I
Error flag output pin Microcontroller interface switching pin (I2C bus/Toshiba bus) GND pin Test pin 0 Test pin 1 ADC-Lch signal input pin 4 ADC-Lch signal input pin 3 ADC-Lch signal input pin 2 ADC-Lch signal input pin 1 ADC-Rch signal input pin 4 ADC-Rch signal input pin 3 ADC-Rch signal input pin 2 ADC-Rch signal input pin 1 Analog ground pin for ADC-Lch Lch analog line-out pin Reference voltage pin for ADC-Lch Analog power pin for ADC-L/Rch Reference voltage pin for ADC-Rch Rch analgo lline-out pin Analog ground pin for ADC-Rch
Open drain output Schmitt input
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
58 59 60 61 65 66 67 68 69 70 71 72 74 75 76 78 79 80 1
I I I I I I I I I I
O I
I O
Note 2: 28 to 33 pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are 39 to 41 pins and 43 to 46 pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
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TC94A04AFG/AFDG
Explanation of Block Operations
1. Explanation Pin Operations
Pin No. TC94A 04AFG 2 3 TC94A 04AFDG (Note 3) 3 4 Symbol Function
XI XO
Master mode: Connect the crystal oscillator Slave mode: Supplies an external master clock to XI. Master clock is 768 fs. Each master-clock frequency to fs is as follows. fs 32 kHz 44.1 kHz 48 kHz 96 kHz 768 fs 24.576 MHz 33.868 MHz 36.864 MHz 36.864 MHz
1, 4 to 25 26 27 28 29
2, 5 to 35 37 38 39 40
Omitted VDDR GNDR SYNC ELRI/O Power pin for delay RAM Ground pin for delay RAM Program SYNC signal input pin
LR clock pin for serial data input (DIN)/serial data output (DOUT). When you carry out a slave operation to a serial input/output data, please set it as an input. And when you carry out a master operation, please set it as an output (command 43h: SIOS). Output frequency can perform selection of 1 fs/2 fs by ELRQS (command: 40h).
30
41
EBCI/O
Bit clock pin for serial data input (DIN)/serial data output (DOUT). When you carry out a slave operation to a serial input/output data, please set it as an input. And when you carry out a master operation, please set it as an output (command 43h: SIOS). Output frequency can be select as follows by EBCQS (command: 40h). EBCQS [1:0] 0 1 2 3 Output Frequency 32 fs 64 fs 128 fs for test
31 32 33 34
43 45 46 48
DIN2 DIN1 DIN0 DOUT
Serial data input pin. The serial data of a total of 6-channels can be inputted. Switching of the number of channel is set by CHSI (command: 42h). Moreover, switching of master/slave function is set by SIS (command: 42h) Serial data output pin. Connected to internal register for output in DSP block. The internal register connected is set up by CHSO (command: 43h).
35 36
49 50
VDD RST
Power pin Reset pin. "L" at initialization.
Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
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TC94A04AFG/AFDG
Pin No. TC94A 04AFG 37 38 39 40 41 42 TC94A 04AFDG (Note 3) 52 53 54 55 57 58 Symbol Function
CS IFCK IFDI IFDO ERR I2CS
Microcontroller interface pin I2CS 0 1 Transmission Mode Toshiba original bus mode I2C bus mode
Toshiba Original Bus Mode CS IFCK IFDI IFDO ERR Chip select Transmit/receive clock Data/command input Data output (monitor data) Error flag signal output (for runaway detector)
I C Bus Mode Chip select (can be fixed to "L") Transmit/receive clock Data input/output Fixed to "L" level output Error flag signal output (for runaway detector)
2
43 44 45 46 47 48 49 50 51 52 53 54 to 60
59 60 61 65 66 67 68 69 70 71 72 74 to 80, 1
GND TST0 TST1 LIN4 LIN3 LIN2 LIN1 RIN4 RIN3 RIN2 RIN1 Omitted
Ground pin Test pin. Fixed to "L"
Four channel analog L-ch input pin. Incorporates an analog selector. And an input switching is selected by Command AIS (command: 42h) (MIX is also possible). The selected signal is outputted from OUTL (55 pin).
Four channel analog R-ch input pin. Incorporates an analog selector. And an input switching is selected by Command AIS (command: 42h) (MIX is also possible). The selected signal is outputted from OUTR (59 pin).
Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to VDD or GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
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TC94A04AFG/AFDG
2. Microcontroller Interface
2.1 Standard Transmission Mode
When I2CS = "L", data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI signal on the IFCK signal rising edge. When CS = "H", the IFCK and IFDI signals are don't care.
2.1.1 Setting Resisters
CS IFCK IFDI
C7 C5 C3 C1 C0 D15 D13 D11 D9 D14 D12 D10 D8 D7 D5 D3 D1 D0
Don't care
C6
C4
C2
D6
D4
D2
Don't care
Cn: COMMAND Dn: Data
The registers are set by command using the IFDI signals. The first byte is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB. Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be switched, such as the RUN-MUTE command (command-44h) or the IFF flag (command-4Ah), must be synchronized with the SYNC signal and loaded on that signal.
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TC94A04AFG/AFDG
2.1.2 Setting RAM (sequential)
CS IFCK IFDI
C7 C5 C3 C1 C0 A15 A13 A11 A9 A14 A12 A10 A8 A7 A5 A3 A1 A0 D15 D13 D11 D9 D14 D12 D10 D8 D1 D0
Don't care
C6
C4
C2
A6
A4
A2
Don't care Cn: COMMAND An: ADDRESS Dn: Data
The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field following the RAM address bytes is 2 x n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous.
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TC94A04AFG/AFDG
2.1.3 Setting RAM (ACMP mode)
CS IFCK IFDI
C7 C5 C3 C1 C0 A15 A13 A11 A9 A14 A12 A10 A8 A7 A5 A3 A1 A0 D15 D13 D11 D9 D14 D12 D10 D8 D7 D5 D3 D1 D0 D1 D0
Don't care
C6
C4
C2
A6
A4
A2
D6
D4
D2
Don't care Cn: COMMAND An: ADDRESS Dn: Data
In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC94A04AFG/AFDG is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. The length of the data field is 2 x n bytes, where n < 32. = In addition, operation at the time of transmitting other commands, before package rewriting of the data by ACMP mode was completed cannot be guaranteed. Please set up again after initializing by RST terminal or the initialization command.
K1 K2 K6 K4 K7
+
+
K9 MCU-I/F IFB-RAM CRAM
Write one by one K3 K5 K8 K10
Update for 1 fs
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TC94A04AFG/AFDG
2.2 I C Bus Mode
When I2CS = "H", data can be transmitted or received in I2C bus mode. When the CS signal is Low, control from the microcontroller is enabled. In I2C mode, the CS signal can be used fixed to "L". The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI data on the IFCK signal rising edge. When CS = "H", IFCK and IFD signal are don't care.
2
2.2.1 Setting Registers
start CS IFCK IFDI (MCU ) 32h HZ HZ HZ HZ end
A7
A5
A3
A1 A0
C7
C5
C3
C1 C0
D15 D13 D11 D9 D14 D12 D10 D8
D7
D5
D3 D2 2
A6
A4
A2
C6
C4
C2
D6
D4
An: I C address Cn: COMMAND Dn: Data
The registers are set by command data using the IFDI signal. The first byte after the I2C address (= 32h) is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C format. The data loaded internally every two bytes. Note that commands or data that must be switched on the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be synchronized with the SYNC signal and loaded on that signal.
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TC94A04AFG/AFDG
2.2.2 Setting RAM (sequential)
start CS IFCK IFDI (MCU ) 32h HZ HZ HZ HZ HZ end
A7
A5
A3
A1 A0
C7
C5
C3
C1 C0
RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8
RA7 RA5 RA3 RA1 RA6 RA4 RA2 RA0
D15 D13 D11 D9 D14 D12 D10 D8
A6
A4
A2
C6
C4
C2
Cn: COMMAND 2 An: I C address RAn: RAM-ADDRESS Dn: Data
The RAMs are set by command data using the IFDI signal. The first byte after the I2C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM. The length of the data field following the RAM address bytes is 2 x n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous.
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TC94A04AFG/AFDG
2.2.3 Setting RAM (ACMP mode)
start CS IFCK IFDI (MCU ) 32h HZ HZ HZ HZ HZ HZ end
A7
A5
A3
A1 A0
C7 C5 C3 C6
C1
RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8
RA7 RA5 RA3 RA1 RA6 RA4 RA2 RA0
D15 D13 D11 D9 D14 D12 D10 D8
A6
A4
A2
C4 C2 C0
Cn: COMMAND 2 An: I C address RAn: RAM-ADDRESS Dn: Data
In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC94A04AFG/AFDG is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. The length of the data field is 2 x n bytes, where n < 32. = In addition, operation at the time of transmitting other commands, before package rewriting of the data by ACMP mode was completed cannot be guaranteed. Please set up again after initializing by RST terminal or the initialization command.
K1 K2 K6 K4 K7
+
+
K9 MCU-I/F IFB-RAM CRAM
Write one by one K3 K5 K8 K10
Update for 1 fs
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TC94A04AFG/AFDG
3. Control Commands
The following table lists the control commands that can be used from the microcontroller.
3.1
Control-Command Table
Table 1
Command TIMING BOOT DIN/AIN DOUT/AOUT RUN-MUTE MSEQ CRAM CRAM-ACMP ORAM ORAM-ACMP IFF DE-EMPH DAC-LR DAC-CS DF-ATT M-RST Code 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh W R/W Timing
Control commands
Description RAM Sequential Transfer Sync/Async to SYNC Signal Async Async Async Async Sync Sync: RUN, Async: STOP Async Sync: RUN, Async: STOP Async

Self boot ROM start address Setting digital/analog input Setting digital/analog output Program execution, mute Sequential RAM CRAM CRAM (ACMP mode) ORAM ORAM (ACMP mode) IFF setting De-emphasis DAC output trim level (L/R-ch) DAC output trim level (C/S-ch) DF attenuator level (all ch) Initialization
Enable

Sync Sync Sync Sync Async Async
Note 4: The command which is "Sync" in the transfer Sync with Sync signal needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It need more than 22.68 s at fs = 44.1 KHz.)
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TC94A04AFG/AFDG
3.2 Control Commands Description
Each command explanation is shown below. *mark in each command explanation table shows the initial value at the time of reset.
Command-40h (0100 0000): TIMING (4400h*)
D15 0 D14 D13 D12 SYD0 D11 0 D10 SYPA D9 SYA1 D8 SYA0 D7 0 D6 SYPS D5 SYS1 D4 SYS0 D3 0 D2 ELROS D1 EBCOS1 D0 EBCOS0
SYPD SYD1
Bit D15 D14
Name
Description Fixed to 0 (zero) ASP digital block sync polarity switching
Value
Operation
SYPD
0 1* 0*
ASP program starts on falling edge ASP program starts on rising edge Signal after SYNC 1 fs output Signal after SYNC 2 fs output 2 fs (for 96 kHz sampling) SYNC pin ELRI/O pin
D13 D12
SYD [1:0]
ASP digital block SYNC signal input switching
1 2 3
D11 D10
SYPA
Fixed to 0 (zero) DF block sync polarity switching
0 1* 0* DF-processing starts in a falling DF-processing starts in a rising SYNC 1 fs output SYNC 2 fs output Reserved Reserved
D9 D8
SYA [1:0] DF block sync input switching
1 2 3
D7 D6
SYPS
Fixed to 0 (zero) SYNC circuit input polarity switching (SYNC reference signal)
0* 1 0* Reference input = L Lch Reference input = H Lch Internal divided results SYNC pin ELRI/O pin
D5 D4
SYS [1:0]
SYNC circuit input switching (SYNC reference signal)
1 2 3
Output ELRI/O pin input divided by 2 (for 96 kHz sampling)
D3 D2
ELROS
Fixed to 0 (zero) Select the clock at the time of ELRI/O output
0* 1 0* 1 fs (Internal fs) 2 fs (Internal fs x 2) 32 fs (Internal fs x 32) 64 fs (Internal fs x 64) 128 fs (Internal fs x 128) Reserved
D1 D0
EBCOS [1:0]
Select the clock at the time of EBCI/O output
1 2 3
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TC94A04AFG/AFDG
Command-41h (0100 0001): BOOT (0000h*)
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 BTA8 D7 BTA7 D6 BTA6 D5 BTA5 D4 BTA4 D3 BTA3 D2 BTA2 D1 BTA1 D0 BTA0
Bit D15 to D7 D8 to D0
Name
Description
Value
Operation
BTA [8:0]
Fixed to 0 (zero)
Self-boot ROM start address
000h to Starts self-boot operation from specified address 1FEh
Command-42h (0100 0010): DIN/AIN (0100h*)
D15 CHSI 1 D14 CHSI 0 D13 VS D12 AUTO D11 AIS4 D10 AIS3 D9 AIS2 D8 AIS1 D7 ZDE D6 SIS D5 D4 D3 D2 D1 D0
ISLT1 ISLT0 IBCS1 IBCS0 IFMT1 IFMT0
Bit
Name
Description
Value 0* Analog 2 ch input
Operation
D15 D14
CHSI [1:0]
Serial input (SI) switching
1 2 3
Digital 4 ch input (2 ch input by the program is possible) Digital 6 ch input Analog and Digital MIX mode CMOS level TTL level Mute OFF Mute ON AIS4: LIN4/RIN4 pin, AIS3: LIN3/RIN3 pin, AIS2: LIN2/RIN2 pin, AIS1: LIN1/RIN1 pin Select channel, it was set as "1". (output from OUTL/OUTR) MIX between channels is also possible. Mute OFF Mute ON Master (synchronizes with internal clock (output from ELRI/O EBCI/O pin)) Slave (synchronizes with external clock (input from ELRI/O EBCI/O pin)) 16 slots (bit clock = 32 fs) 20 slots (bit clock = 40 fs) 24 slots (bit clock = 48 fs) 32 slots (bit clock = 64 fs) 16 bits 18 bits 20 bits 24 bits Pads from the beginning Pads from the end I2S format
D13
VS
Switching threshold of input pin [SYNCELRI/OEBCI/O DIN2DIN1DIN0] Auto mute (analog input)
0* 1 0* 1 0 to Fh (1*)
D12 D11 D10 D9 D8 D7
AUTO
AIS [4:1]
Switching analog input
ZDE
Digital-input zero-level detection mute function
0* 1 0*
D6
SIS
Serial input 1 0*
D5 D4
ISLT [1:0]
Number of serial input slots
1 2 3 0*
D3 D2
IBCS [1:0]
Serial input bit length
1 2 3 0*
D1 D0
IFMT [1:0]
Serial input format
1 2 3
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Command-43h (0100 0011): DOUT/AOUT (0080h*)
D15 0 D14 0 D13 0 D12 HSMP D11 0 D10 0 D9 SIOS D8 SOS D7 D6 D5 D4 D3 D2 D1 D0
CHSO CHSO OSLT 1 0 1
OSLT OBCS OBCS OFMT OFMT 0 1 0 1 0
Bit D15 to D13 D12 D11 D10 D9
Name
Description
Value
Operation
Fixed to 0 (zero)
0* 1 Normal rate High sampling rate
HSMP
Switching high sampling of analog output Fixed to 0 (zero) Switching input/output of ELRI/O, EBCI/O pin
0* 1 0* Input Output
SIOS
D8
SOS
Serial output 1 0
Master (synchronizes with internal clock (output from EBLRI/O, EBCI/O pin)) Slave (synchronizes with external clock (input from EBLR/O, EBCI/O pin)) DOUT pin SIR0 DOUT pin SIR1 DOUT pin SIR2 Reserved 16 slots 20 slots 24 slots 32 slots 16 bits 18 bits 20 bits 24 bits Pads from the beginning Pads from the end I2S format
D7 D6
CHSO [1:0] Serial output switching
1 2* 3 0*
D5 D4
OSLT Number of serial input slots [1:0]
1 2 3 0*
D3 D2
OBCS [1:0] Serial output bit length
1 2 3 0*
D1 D0
OFMT Serial output format [1:0]
1 2 3
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Command-44h (0100 0100): RUN-MUTE (1F0Fh*)
D15 RUN D14 0 D13 0 D12 AD MUT D11 IMUTE D10 OMU TE2 D9 OMU TE1 D8 OMU TE0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
ERDET ZST
SYRC SYRO
Bit D15 D14 D13 D12
Name RUN
Description ASP program execution
Value 0* 1 Stops program Runs program
Operation
Fixed to 0 (zero)
0 1* Mute OFF Mute ON Mute OFF Mute ON Mute OFF Mute ON Mute OFF Mute ON Mute OFF Mute ON
ADMUT
ADC mute
D11
IMUTE
ASP block input mute ASP block output mote
0 1* 0 1* 0 1* 0 1*
D10
OMUTE2 (SIR2 register mute) ASP block output mute (SIR1 register mute)
D9
OMUTE1
D8 D7 to D4 D3
OMUTE0
ASP block output mute (SIR0 register mute)
0
Fixed to 0 (zero)
0 Disable Enable 2-cycle access 1-cycle access Does not reset Reset Does not reset Reset
ERDET
Error detection 1* Switches to access CROM using Log-Linear adjustment Set CP at each SYNC 0 1* 0 1*
D2
ZST
D1
SYRC
D0
SYRO
Set OFP at each SYNC
0 1*
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Command-45h (0100 0101): MSEQ
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 D0
MSA2 MSA1 MSA0
Bit D15 to D3 D2 to D0
Name
Description
Value
Operation
MSA [2:0]
Fixed to 0 (zero)
0h to 7h
Module sequential RAM first address
The address of the head to write in is set up.
D15 0
D14 0
D13 0
D12 0
D11 0
D10 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ 9 8 7 6 5 4 3 2 1 0
Bit D15 to D10 D9 to D0
Name
Description
Value
Operation
MSEQ
Fixed to 0 (zero)
Module sequential RAM data [9:0]
000h to The data written in module sequence RAM are set up. 3FFh
Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)-- data (2 bytes) (module sequential RAM: 8 words)
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TC94A04AFG/AFDG
Command-46h (0100 0110): CRAM
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0
CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM A8 A7 A6 A5 A4 A3 A2 A1 A0
Bit D15 to D9 D8 to D0
Name
Description
Value
Operation
CRAMA [8:0]
Fixed to 0 (zero)
CRAM (coefficient RAM) head address
000h CRAM address of the head at the time of writing in by 46h to command is set up. 17Fh
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit D15 to D0
Name CRAMD [15:0]
Description
Value
Operation
CRAM data
7FFFh to Set CRAM data (two-complement-form formula) 8000h
The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 46h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)--data (2 bytes) (CRAM: 384 words)
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Command-47h (0100 0111): CRAM-ACMP
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0
CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM A8 A7 A6 A5 A4 A3 A2 A1 A0
Bit D15 to D9 D8 to D0
Name
Description
Value
Operation
CRAMA [8:0]
Fixed to 0 (zero)
CRAM (coefficient RAM) head address
000h CRAM address of the head at the time of writing in by 47h to command is set up. 17Fh
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM CRAM D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit D15 to D0
Name CRAMD [15:0]
Description
Value
Operation
CRAM data
7FFFh to Set CRAM data (two-complement-form formula) 8000h
It is CRAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 47h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)--data (2 bytes) (CRAM: 384 word)
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TC94A04AFG/AFDG
Command-48h (0100 1000): ORAM
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
ORAM ORAM ORAM ORAM A3 A2 A1 A0
Bit D15 to D4 D3 to D0
Name
Description
Value
Operation
ORAMA [3:0]
Fixed to 0 (zero)
0h to Fh
ORAM (offset RAM) head address
ORAM address of the head at the time of writing in by 48h command is set up.
D15 0
D14 0
D13 0
D12 0
D11 0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit D15 to D11 D10 to D0
Name
Description
Value
Operation
ORAMD [10:0]
Fixed to 0 (zero)
000 to Set ORAM data 7FFh
ORAM data
It is ORAM write-in command which used the address compare mode. The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 48h-ORAM address (2 bytes)-data (2 bytes)-data (2 bytes)--data (2 bytes) (ORAM: 16 words)
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Command-49h (0100 1001): ORAM-ACMP
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
ORAM ORAM ORAM ORAM A3 A2 A1 A0
Bit D15 to D4 D3 to D0
Name
Description
Value
Operation
ORAMA [3:0]
Fixed to 0 (zero)
0h to Fh
ORAM (offset RAM) head address
ORAM address of the head at the time of writing in by 48h command is set up.
D15 0
D14 0
D13 0
D12 0
D11 0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM ORAM D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit D15 to D11 D10 to D0
Name
Description
Value
Operation
ORAMD [10:0]
Fixed to 0 (zero)
000 to Set ORAM data 7FFh
ORAM data
The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 49h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)--data (2 bytes) (ORAM: 16 words)
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Command-4Ah (0100 1010): IFF (0000h*)
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 IFF2 D1 IFF1 D0 IFF0
Bit D15 to D4 D3
Name
Description
Value
Operation
Fixed to 0 (zero)
0* 1 IFFn = 0 IFFn = 1
IFF2
Set IFFn (n = 2, 1, 0)
Command-4Bh (0100 1011): DE-EMPH (0000h*)
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0
DEMP DEMP 1 0
Bit D15 to D2
Name
Description
Value
Operation
Fixed to 0 (zero)
0* De-emphasis Off fs = 32 kHz fs = 44.1 kHz fs = 48 kHz
D1 DEMP [1:0] D0 Set de-emphasis
1 2 3
Command-4Ch (0100 1100): DAC-LR (1F1Fh*)
D15 0 D14 0 D13 0 D12 ATTL 4 D11 ATTL 3 D10 ATTL 2 D9 ATTL 1 D8 ATTL 0 D7 0 D6 0 D5 0 D4 ATTR 4 D3 ATTR 3 D2 ATTR 2 D1 ATTR 1 D0 ATTR 0
Bit D15 to D13 D12 to D8 D7 to D5 D4 to D0
Name
Description
Value
Operation
Fixed to 0 (zero)
Code : 00h 01h 02h

18h 19h 1Fh ca.-60
ATTL [4:0] DAC L-ch attenuator value
00h to 1Fh*
ATT (dB) : 0 Initial value: 1Fh
-1
-2
-24 ca.-60
Fixed to 0 (zero)
Code : 00h 01h 02h

18h 19h 1Fh ca.-60
ATTR [4:0] DAC R-ch attenuator value
00h to 1Fh*
ATT (dB) : 0 Initial value: 1Fh
-1
-2
-24 ca.-60
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Command-4Dh (0100 1101): DAC-CS (1F1Fh*)
D15 0 D14 0 D13 0 D12 ATTC 4 D11 ATTC 3 D10 ATTC 2 D9 ATTC 1 D8 ATTC 0 D7 0 D6 0 D5 0 D4 ATTS 4 D3 ATTS 3 D2 ATTS 2 D1 ATTS 1 D0 ATTS 0
Bit D15 to D13 D12 to D8 D7 to D5 D4 to D0
Name
Description
Value
Operation
Fixed to 0 (zero)
Code : 00h 01h 02h

18h 19h 1Fh ca.-60
ATTC [4:0] DAC C-ch attenuator value
00h to 1Fh*
ATT (dB) : 0 Initial value: 1Fh
-1
-2
-24 ca.-60
Fixed to 0 (zero)
Code : 00h 01h 02h

18h 19h 1Fh ca.-60
ATTS [4:0] DAC-Sch attenuator value
00h to 1Fh*
ATT (dB) : 0 Initial value: 1Fh
-1
-2
-24 ca.-60
Command-4Eh (0100 1110): DF-ATT (007Fh*)
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 ATL6 D5 ATL5 D4 ATL4 D3 ATL3 D2 ATL2 D1 ATL1 D0 ATL0
Bit D15 to D7
Name
Description
Value
Operation
Fixed to 0 (zero)
Initial value: 7Fh (level = -) LEVEL = 20 x log (ATL/128)
Code 00h 01h 02h to D6 to D0 ATL [6:0] DF attenuator value 00h to 7Fh* 0Dh 1Ah 25h to 3Fh to 7Dh 7Eh 7Fh
ATL 7Fh 7Eh 7Dh to 72h 65h 5Ah to 40h to 02h 01h 00h
Level 0.00dB
-0.14dB -0.21dB
to
-1.01dB -2.06dB -3.06dB
to
-6.02dB
to
-36.12dB -42.14dB -
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Command-4Fh (0100 1111): M-RST (0000h*)
D15 MRST D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
Bit D15 D14 to D0
Name MRST
Description Initialization from the micro controller command
Value 0* 1 Does not initialize
Operation
Initializes (set to initial value (0*))
Fixed to 0 (zero)
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4. Self-Boot Function Description
4.1 Self-Boot Function
The TC94A04AFG/AFDG supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later. The microcontroller interface circuit supports two format: I2C and the original mode. However, the boot must be executed in Standard Transmission.
RST
Self-boot Circuit BTCSN BTIFCK BTIFDI BTMODE
Microcontroller Interface Circuit CS IFCK IFDI
SBROM (512 word x 18 bit)
Timing generat or
1
0
1
0
1
0 Internal I2CS I2CS
Internal IFDI
Internal IFCK
Internal CSN
Figure 1 Self-Boot System
All the command inputs from the exterior are disregarded during a boot term.
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4.2 Boot ROM Format
The following shows the breakdown of the 18 bits.
00 01 10 11 Data that are being sent Command Final data (after the data are sent, the CS signal set to "H"). Jump address (jump to any address in the boot-ROM)
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (MSB) 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 0 11 11 01 10 01 00 00 00 00 10 11 Data Data Data Data Data Address Data CMD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSB) 0 0 All `0' JMP JMP CMD Data (last) CMD Data (cont) Data (cont) Data (cont) Data (cont) Data (last) JMP 1FFh
Address Address CMD
1FFh
11
Address
JMP 1FFh
Figure 2 Boot ROM Format and Example
Note 5: Boot mode completes when the address reaches 1FFh, the maximum value. Therefore, for the final address (1FFh), write JMP 1FFh (data = 301FFh). Note 6: For the head address (000h), write (00000). Note 7: Please do not set a command of fs synchronous taking in to the address: 1FEh (RUN-MUTE/IFF/DE-EMPH/DAC-LR/DAC-CS etc.).
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4.3 Self-Boot Operation
Self-boot operation supports two modes: one for use at reset and for setting the microcontroller.
4.3.1 Self-Boot Operation at Reset
To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4 ms when fs = 44.1 kHz) after a reset release is wait period. The boot operation starts at the end of this period.
Relationship between fs and Wait Period
fs 32 kHz 44.1 kHz 48 kHz 96 kHz Wait Period 64.0 ms 46.4 ms 42.7 ms Boot Time (maximum) 16.0 ms 11.6 ms 10.7 ms
Starting address is fixed to 001h. If the jump address to application to execute at the time of a boot is specified to be 0001h, at the time of a reset, the initial value of application will be set up automatically. When you do not boot at the time of a reset, please set JMP (1FFh: data = 301FFh) as 001h.
4.3.2 Self-Boot Operation When Setting Microcontroller
In this mode, the microcontroller can specify any address and the boot operation starts from that address. The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The boot operation when set from the microcontroller is the same as the self-boot operation at reset except that the boot operation can start from any address.
Boot wait period 2048 fs RST FS BTMODE (internal signal) BootRom Adrs Rom Dt [17:16] BTCSN BTIFCK BTIFDI C D D D C D C DT: Data DE: DataEnd 2 JMP 10 11 12 13 14 15 16
CMD
Boot period 512 fs (max)
3FF
JMP
DT DT DE
CMD
DE
CMD
JMP
8 clock
C
Figure 3 Boot Timing Chart (at reset)
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5. Cautions on Use
5.1 Initial Reset
After a power-supply injection, once at least, please set up a required register after applying reset which makes RST terminal "L" level and making the value of an internal register decide.
5.2
The Cautions at the Time of Using ACMP (address compare mode)
In rewriting coefficient data and offset data using ACMP mode, please do not use it the following condition.
5.2.1 Please Do Not Transmit the Following Command before Completing Rewriting of Data.
Please do not send the following command before completing rewriting of data of CRAM or ORAM. Please check that waiting the term after rewriting has been completed until it transmits the following was carried out.
5.2.2 Please Do Not Include Data of an Intact Address.
Please do not include coefficient data of offset data of address which are not used by the program under execution, into transmitting data. When data of an intact address is contained, operation in ACMP mode cannot de ended. If the following command is transmitted in this state, RAM data will become unfixed also by the command with the command unrelated to CRAM or ORAM. It needs to reset and all data needs to be re-set up to interrupt before completing rewriting of data in the rewriting processing.
5.2.3 Please Do Not Use the 0th Street of CRAM Address. 5.3 Please Do Not Perform Continuation Transmission over the 0th Address.
The transmission over the 0th address may incorrect-operate. For example, when writing in 17Fh from 178h and 000h from 007h of CRAM, it must transmit in two steps.
5.4
Please Do Not Set-Up a Soft Reset Command as the Data of Boot ROM.
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Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation TC94A04AFG TC94A04AFDG Operating temperature Storage temperature Symbol VDD Vin PD Topr Tstg Rating Unit V V mW C C
-0.3 to 6.0 -0.3 to VDD + 0.3
1538 1538 (Note 8)
-40 to 75 -55 to 150
Note 8: Power dissipation of TC94A04AFG is reference value when assembled chip on PCB. (normally, PD is 1250 mW.)
Electrical Characteristics
DC Characteristics
Characteristics Operating power supply voltage Operating frequency range Operating power supply current
(unless otherwise specified, Ta = 25C, VDD = VDX = VDR = VDA12 = VDA23 = VDALR = 5.0 V)
Symbol VDD fopr IDD
Test Circuit
Test Condition Ta = -40 to 75C 511 step mode fopr = 36.864 MHz 511 Step mode
Min 4.75 12
Typ. 5.0 33.8 135
Max 5.25 37 146
Unit V MHz mA

Clock Pins (XI, XO)
Characteristics "H" level Input voltage (1) "L" level "H" level Output voltage (1) "L" level VIL1 VOH1 VOL1 IOH = -3.0 mA IOL = 5.0 mA Symbol VIH1 Test Circuit Test Condition Min VDD x 0.7 Typ. Max VDD + 0.3 VDD x 0.7 Unit

XI pin
V
VDD - 0.5
V 0.5
XO pin
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Input Pins
Characteristics "H" level Input voltage (2) "L" level "H" level Input voltage (3) "L" level Input leakage current "H" level "L" level VIL3 IIH2 IIL2 VIL2 VIH3 Symbol VIH2 Test Circuit Test Condition Min VDD x 0.8 Typ. Max Unit
(Note 9) (CMOS input), (Note 10)

V VDD x 0.2
VDD x 0.5
V VDD x 0.2 10
(Note 9) (TTL input)

VIN = VDD VIN = 0 V (Note 9), (Note 10), (Note 11)
-10
A
Note 9: SYNC, ELRI/O, EBCI/O, DIN0 to 2 Note 10: CS , IFCK, IFDI, I2CS, TST0, TST1
Note 11: XI
Output Pins
Characteristics "H" level Output voltage (2) "L" level Output voltage (3) "L" level Output open leakage current VOL2 VOL3 IOZ4 Symbol VOH2 Test Circuit Test Condition IOH = -2.0 mA (Note 12) (Note 12), (Note 14) (Note 13) (Note 12), (Note 14) Min VDD - 0.5 Typ. Max Unit

V 0.5 0.5 V
IOL = 2.0 mA

IOL = 4.0 mA VOH = VDD
10
A
Note 12: DOUT, IFDO (normally output) Note 13: IFDI (I C mode output) Note 14: IFOK, ERR (open drain output)
2
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AC Characteristics
AD Converter: LIN1 to LIN4, RIN1 to RIN4 Pins
Characteristics Symbol Test Circuit Test Condition Input level that ADC output at full-scale digital output (Note 15) Each of LIN1 to LIN4, RIN1 to RIN4 pins A-Weight, X'tal: 36.864 MHz CCIR-ARM, X'tal: 36.864 MHz 20 kHz LPF, X'tal: 36.864 MHz (Note 15) (Note 15) (Note 15) Min Typ. Max Unit
Maximum input signal level
Vin

1.27
1.33
-70 -72
Vrms
Input impedance
Zin S/Na1
87 83
19 95 91
k dB dB dB
S/(N + D) ratio S/Na2 THD + N THDa

-82 -80
Cross-talk
CTa
20 kHz LPF, Lch Rch/Rch Lch, X'tal: 36.864 MHz (Note 15) A-Weight, X'tal: 36.864 MHz (Note 15)
dB
Dynamic range
DRa
83
90
dB
Note 15: One input pin selected of four selector of each channels.
Selector Output: OUTL, OUTR Pins
Characteristics Output signal level Output impedance S/(N + D) ratio THD + N Cross-talk Symbol Vout Zout S/Ns THDs CTs Test Circuit Test Condition 1 kHz, 1.122 Vrms input (Note 15) OUTL/OUTR pins A-Weight 20 kHz LPF OUTL OUTR/ OUTR OUTL Min 0.9 Typ. 1.0 0.5 104 Max 1.12 Unit Vrms k dB dB dB

93
-80 -80

-94 -88
Note 15: One input pin selected of four selectors of each channels.
DA Converter
Characteristics Output signal level S/N ratio THD + N Cross-talk Dynamic range Symbol Ao S/Nd THDd CTd DRd Test Circuit Test Condition Output voltage at full-scale digital input A-Weight, X'tal: 36.864 MHz 20 kHz LPF, X'tal: 36.864 MHz 20 kHz LPF, X'tal: 36.864 MHz A-Weight, X'tal: 36.864 MHz Min 1.22 90 Typ. 1.27 98 Max 1.37 Unit Vrms dB dB dB dB

-75 -83

87
-86 -95
95
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Timing
Clock Input Pin (XI)
Characteristics Clock cycle Clock "H" cycle width Clock "L" cycle width Symbol tXI tXIH tXIL Test Circuit Test Condition Min 27 Typ. Max Unit ns ns ns

13.5 13.5

Reset Pin ( RST )
Characteristics Standby time Reset pulse width Symbol tRRS tWRS Test Circuit Test Condition Min 10 1.0 Typ. Max Unit ms

s
Audio Serial Interface (EBCI/O, ELRI/O, DIN0 to 2, DOUT)
Characteristics ELRI/O hold time (ELRI/O input) DIN 0, 1, 2 setup time DIN 0, 1, 2 hold time EBCI/O clock cycle EBCI/O clock "H" cycle width EBCI/O clock "L" clock width ELRI/O output delay time (ELRI/O output) DOUT output delay time (1) DOUT output delay time (2) tLOH tDO1 tDO2 (ELRI/O input) Symbol tLIH tSDI tHDI tEBCI Test Circuit Test Condition Min Typ. Max 75 Unit ns ns ns ns

Unless than fs = 48 kHz,
-75
50 50 EBCI/O input: Unless than 64 fs 150

tEBIH
75
ns
tEBIL
75
ns

CL = 30 pF CL = 30 pF CL = 30 pF
0

60 35 35
ns ns ns

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Microcontroller Interface
(1) Standard transmission mode ( CS , IFCK, IFDI, IFDO)
Test Circuit
Characteristics Standby time CS -IFCK setup time IFCK "L" cycle width IFCK "H" cycle width IFCK - CS setup time CS "H" cycle width IFDI-IFCK setup time IFCK -IFDI holed time IFCK -IFDO propagation delay time
Symbol tSTB tCCD tWLC tWHC tCKC tWCS tSCD tHCD tDDO
Test Condition
Min 1.0 0.2 0.25 0.25 0.25
Typ.
Max
Unit

CL = 30 pF

(Note 16)

0.2
s s s s s s s s s
0.5 0.2 0.2

Note 16: The command which is "Sync" in the transfer Sync with Sync signal of a 14 page table 1 control command table needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It needs more than 22.68 s at fs = 44.1 KHz.)
(2)
I2C mode ( CS , IFCK, IFDI)
Test Circuit
Characteristics IFCK clock frequency IFCK "H" cycle width IFCK "L" cycle width Data setup time Data hold time Transmission start condition hold time Repeat transmission start setup time Transmission end condition setup time Data transmission interval I C rising time I C falling time
2 2
Symbol tIFCK tH tL tDS tDH tSCH tSCS tECS tBUF tR tF
Test Condition CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF
Min 0 0.6 1.3 0.1 0 0.6 0.6 0.6 1.3
Typ.
Max 400
Unit kHz

0.3 0.3
s s s s s s s s s s

35
2005-09-28
TC94A04AFG/AFDG
AC Characteristic Measurement Point
(1) Clock pin (XI)
XI 50% tXIH tXI tXIL
(2)
Reset
100% VDD 0% RST tRRS 50% tWRS 90%
(3)
Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT)
tEBCI tEBIL tEBIH
ELRI/O (I)
EBCI/O (I)
DIN02
tLIH
tSDI tEBCO tEBOL
tHDI
tLIH
tEBOH
ELRI/O (O)
EBCI/O (O)
DOUT
tLOH
tDO1
tDO2
tLOH
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2005-09-28
TC94A04AFG/AFDG
(4)
RST
Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO)
CS
tSTB tCCD CS tWLC tWHC tCKC tWCS
IFCK
IFDI tSCD IFDO tDDO tHCD
(5)
Microcontroller interface in I2C mode (IFCK, IFDI)
tBUF
IFDI
IFCK
tSCH
tR
tL
tH
tDS
tDH
tSCS
tF
tECS
37
2005-09-28
TC94A04AFG/AFDG
Peripheral Circuit Example 1
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
MCU I/F
1 k Lch (LIN4)
4.7 F
2200 pF 4.7 F 45 TST1 2200 pF 44 TST0 43 GND 42 I2CS 41 ERR 40 IFDO 39 IFDI 38 IFCK 37 CS 36 RST 35 VDD 34 DOUT 33 DIN0 32 DIN1 31 DIN2 EBCI/O (O) 30 ELRI/O (O) 29
1 k Rch (RIN4)
1 k Lch (LIN3)
4.7 F
46 LIN4
2200 pF 4.7 F
47 LIN3
1 k Rch (RIN3)
48 LIN2
0.1 F
47 F
SYNC 28
0.1 F 4.7 F (BP)
50 RIN4 1 k Lch (LIN2) 4.7 F
VDDR 26 GNDA4 25
51 RIN3
0.1 F
2200 pF 4.7 F
1 k Rch (RIN2)
TC94A04AFG (top view) 53 RIN1 AO4 23
2200 pF
54 GNDAL
AOT4 22
55 OUTL 0.1 F 47 F 47 F 56 VRAL
VDA34 21 AOT3 20 4.7 F (BP)
1 k Lch (LIN1)
4.7 F
2200 pF 4.7 F 0.1 F 47 F 47 F
57 VDALR 58 VRAR
AO3 19
0.1 F
1 k Rch (RIN1)
AI3 18
2200 pF
59 OUTR
GNDA3 17
60 GNDAR GNDA1 GNDA2
VRO2 16 47 F
GNDX
VDA12
AO1
560 pF
VDX
AO2
AI1
10 k
1
2 0.1 F 47 F
3
4
5
6
7
8
9
10
11
12
AI2
XI
XO
10 F
13
14 47 F
15 47 F
4.7 F (BP) 0.1 F
4.7 F (BP) 0.1 F
10 k
10 F
560 pF
OUTR
36.8 MHz
47 F
47 F
2.2 M 10 pF
2.2 H
270
270
270
VRI
OUTL
VRO1
AOT1
AOT2
270
47 pF
47 F
47 F
52 RIN2
AI4 24
47 F
2200 pF
49 LIN1
GNDR 27
Analog VDD 1000 pF 2200 pF 2200 pF 2200 pF 2200 pF
Digital VDD
4.7 F
4.7 F
4.7 F
4.7 F
GND Analog GND Digital GND
10 k
10 k
10 k
10 k
AOT1 (L1 out)
AOT2 (R1 out)
AOT3 (L2 out)
AOT4 (R2 out)
38
2005-09-28
TC94A04AFG/AFDG
Peripheral Circuit Example 2
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
MCU I/F
1 k Lch (LIN4)
4.7 F
2200 pF 4.7 F 64 NC 63 NC 62 NC 61 TST1 60 TST0 59 GND 58 I2CS 57 ERR 56 NC 55 IFDO 54 IFDI 53 IFCK 52 CS 51 NC 50 RST 49 VDD 48 DOUT 47 NC 46 DIN0 45 DIN1 44 NC 43 DIN2 42 NC 41 EBCI/O (O)
1 k Rch (RIN4)
2200 pF
0.1 F
47 F
1 k Lch (LIN3)
4.7 F
LIN4
ELRI/O (O) 40
2200 pF 4.7 F
66 LIN3
SYNC 39
0.1 F
Rch (RIN3) 2200 pF 68 LIN1 VDDR 37 NC 36
69 RIN4 1 k Lch (LIN2) 4.7 F
70 RIN3
GNDA4 35
0.1 F
2200 pF 4.7 F
1 k Rch (RIN2)
72 RIN1 TC94A04AFDG (top view) 73 NC
AI4 33
2200 pF
AO4 32
74 GNDAL
NC 31
1 k Lch (LIN1)
4.7 F 47 F 2200 pF 4.7 F 0.1 F 47 F
75 OUTL
AOT4 30
76 VRAL
NC 29
1 k Rch (RIN1)
77 NC
VDA34 28 AOT3 27 4.7 F (BP)
2200 pF 0.1 F 47 F 47 F
78 VDALR 79 VRAR
0.1 F
80 OUTR GNDAR GNDA1 GNDA2 GNDA3 GNDX VDA12 VRO1 VRO2 AOT1 AOT2
AI3 25
AO1
AO2
VDX
AI1
AI2
NC
NC
NC
NC
NC
10 k
10 F
560 pF
1
2
3 0.1 F 47 F
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 47 F
21 47 F
22
NC
XO
XI
OUTL
VRI
23 47 F
24
4.7 F (BP) 0.1 F
4.7 F (BP) 0.1 F
10 k
10 F
560 pF
OUTR
36.8 MHz
47 F
47 F
2.2 M 10 pF
2.2 H
270
270
270
270
47 pF
Analog VDD 1000 pF 2200 pF 2200 pF 2200 pF 2200 pF
Digital VDD +5 V
4.7 F
4.7 F
4.7 F
4.7 F
Analog GND 10 k 10 k 10 k 10 k
Digital GND
AOT1 (L1 out)
AOT2 (R1 out)
AOT3 (L2 out)
AOT4 (R2 out)
39
47 F GND
AO3 26
4.7 F (BP)
47 F
71 RIN2
NC 34
47 F
1 k
67 LIN2
GNDR 38
2005-09-28
TC94A04AFG/AFDG
Package Dimensions
P-QFP60-1414-0.80N U n it: m m
(Note) Palladium plate
Weight: 1.08 g (typ.)
40
2005-09-28
TC94A04AFG/AFDG
Package Dimensions
P-QFP80 -1420-0.80M U n it: m m
(Note) Palladium plate
Weight: 1.57 g (typ.)
41
2005-09-28
TC94A04AFG/AFDG
42
2005-09-28

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